The present invention relates to a semiconductor memory device, and more particularly to a highly integrated dynamic random access memory (DRAM) device.
Along with a recent trend toward attaining further packing density in a semiconductor memory device, the height of a capacitor is increasingly greater in a DRAM cell which is composed of a transistor and the capacitor in order to secure sufficient capacitance within a limited area. This greater height of the capacitor compensates for the decrease in the capacitor area due to the high integration of the semiconductor memory device. This increase in the height of the capacitor unstabilizes step coverage, which is apt to cause disconnection during metal layer formation. An interlayer insulating film formed under the metal layer can be thickened to improve the step coverage. However, thicker interlayer insulating film is liable to induce disconnection of the metal layer due to a deep contact hole during a contact process for allowing the metal layer to contact a predetermined impurity region in a semiconductor substrate. As described above, since the thickness of the interlayer insulating film and the interlayer connection characteristic are mutually related, thickening the thickness of the interlayer insulating film is improper. For the purpose of preventing the disconnection of the metal layer, a technique is suggested in Korean Patent Application No. 90-13003 (Korean Patent Publication No. 91-5462) entitled: "Dynamic Random Access Memory Device" filed by Nippon Electronics Co., Ltd., in which a sloped-sidewall structure is formed in the peripheral side from a lower electrode of a capacitor of a peripheral memory cell in a memory cell array.
FIG. 1 is a sectional view showing a semiconductor memory device manufactured by a conventional technique, which is described in the above patent application.
Here, only two peripheral memory cells in a memory cell array which is formed of each of memory cells connected to intersection of a plurality of bit lines and word lines are illustrated. In a semiconductor substrate 11 of a first conductivity type, first, second and third impurity regions 12a, 15 and 13a of a second conductivity type opposite to the first conductivity type are formed apart from each other by a predetermined distance. The first and third impurity regions 12a and 13a act as a storage node of the memory cell, and the second impurity region 15 is connected to a bit line. Gate electrodes 12c and 13c are formed over the substrate 11 between the impurity regions using gate insulating layers 12b and 13b as respective interlayers. The gate electrodes 12c and 13c form a switching transistor of the memory cell together with the impurity regions 12a, 15 and 13a. Lower electrodes 12d and 13d composed of a polycrystalline silicon contacted with the first and third impurity regions 12a and 13a via contact holes 16a and 16b formed by etching a predetermined portion of a first insulating layer 16 formed on the semiconductor substrate 11 is respectively formed. At this time, a sloped-sidewall structure 17 is formed on the first insulating layer 16 in the outermost portion of the memory cell array, which has a steep inner wall 17a toward the inside of the memory cell array, but has a gently sloped outer wall 17b toward the outside thereof. A peripheral circuit of the semiconductor memory device is formed in the outside of the outer wall 17b. An upper electrode 19 is formed over the lower electrodes 12d and 13d using a dielectric film 18 as an interlayer, thereby forming a capacitor. The switching transistor and capacitor form unit memory cell of the memory cell array. Then, a second insulating layer 20 and a metal layer 21 are formed over the substrate 11, thereby forming the memory cell array.
As illustrated in FIG. 1, by forming the sloped-sidewall structure, the metal layer having an excellent step coverage is formed even though the thickness of the lower electrode and the insulating layer thereon is thickened.
However, an additional photolithography and an etching for forming the slope of the outer wall are needed to form the sloped-sidewall structure. Moreover, since a polycrystalline silicon layer used for forming the sloped-sidewall should be left in the periphery of the memory cell array during forming the lower electrode of the capacitor to form the sloped-sidewall structure, the technique is adopted to only a DRAM cell having a single stack-type capacitor structure. That is, in a DRAM cell having a cylindrical or fin-type capacitor structure, the polycrystalline silicon layer left in the periphery of the memory cell array also has the cylindrical or fin-type shape, thereby impeding the formation of the sloped-sidewall structure. Accordingly, the sloped-sidewall structure is adoptable to only the single stack-type capacitor structure.